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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>H:\nestang\nestang-25k\impl\gwsynthesis\nes.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>H:\nestang\nestang-25k\src\nestang.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>H:\nestang\nestang-25k\src\nes.sdc</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-5</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Oct 30 14:58:19 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.85V -40C ES</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 0.95V 100C ES</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>45493</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>16215</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>117</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>419</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>3808</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>all_inputs</td>
</tr>
<tr>
<td>clk_sdram</td>
<td>Base</td>
<td>40.000</td>
<td>25.000
<td>0.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td>all_outputs</td>
</tr>
<tr>
<td>u_hdmi/clk_audio</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>u_hdmi/clk_audio_s0/Q </td>
</tr>
<tr>
<td>controller/W_scan_seq_pls</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q </td>
</tr>
<tr>
<td>controller/n50_15</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>controller/n50_s1/F </td>
</tr>
<tr>
<td>sclk_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>sclk_s1/Q </td>
</tr>
<tr>
<td>controller/W_TXSET</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>controller/pls/W_TXSET_s/F </td>
</tr>
<tr>
<td>controller2/W_scan_seq_pls</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>controller2/pls/O_SCAN_SEQ_PLS_s0/Q </td>
</tr>
<tr>
<td>controller2/n50_15</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>controller2/n50_s1/F </td>
</tr>
<tr>
<td>controller2/W_TXSET</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>controller2/pls/W_TXSET_s/F </td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Generated</td>
<td>83.333</td>
<td>12.000
<td>0.000</td>
<td>41.667</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0 </td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
<td>Generated</td>
<td>2.667</td>
<td>375.000
<td>0.000</td>
<td>1.333</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>pll_clk/PLLA_inst/CLKOUT2 </td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
<td>Generated</td>
<td>40.000</td>
<td>25.000
<td>0.000</td>
<td>20.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3 </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>sys_clk</td>
<td>50.000(MHz)</td>
<td>91.908(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>clk_sdram</td>
<td>25.000(MHz)</td>
<td>74.559(MHz)</td>
<td>18</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>u_hdmi/clk_audio</td>
<td>100.000(MHz)</td>
<td>449.817(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>controller/n50_15</td>
<td>100.000(MHz)</td>
<td>274.113(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>sclk_6</td>
<td>100.000(MHz)</td>
<td style="color: #FF0000;" class = "error">86.519(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>6</td>
<td>controller/W_TXSET</td>
<td>100.000(MHz)</td>
<td>214.967(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>7</td>
<td>controller2/n50_15</td>
<td>100.000(MHz)</td>
<td>190.363(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>8</td>
<td>controller2/W_TXSET</td>
<td>100.000(MHz)</td>
<td>266.334(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
<tr>
<td>9</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>12.000(MHz)</td>
<td>106.706(MHz)</td>
<td>8</td>
<td>TOP</td>
</tr>
<tr>
<td>10</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
<td>25.000(MHz)</td>
<td>28.268(MHz)</td>
<td>24</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of controller/W_scan_seq_pls!</h4>
<h4>No timing paths to get frequency of controller2/W_scan_seq_pls!</h4>
<h4>No timing paths to get frequency of pll_clk/PLLA_inst/CLKOUT2.default_gen_clk!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sys_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk_sdram</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk_sdram</td>
<td>Hold</td>
<td>-123.795</td>
<td>903</td>
</tr>
<tr>
<td>u_hdmi/clk_audio</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_hdmi/clk_audio</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/W_scan_seq_pls</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/W_scan_seq_pls</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/n50_15</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/n50_15</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sclk_6</td>
<td>Setup</td>
<td>-1.842</td>
<td>4</td>
</tr>
<tr>
<td>sclk_6</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/W_TXSET</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller/W_TXSET</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller2/W_scan_seq_pls</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller2/W_scan_seq_pls</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller2/n50_15</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller2/n50_15</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller2/W_TXSET</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>controller2/W_TXSET</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-5.066</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/state_1_s2/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.028</td>
<td>8.025</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-4.960</td>
<td>usb_controller/game_u_s0/Q</td>
<td>sd_loader/debounce_18_s0/D</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.024</td>
<td>8.170</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-4.885</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/state_0_s1/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.038</td>
<td>7.835</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-4.885</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/state_2_s1/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.038</td>
<td>7.835</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-4.831</td>
<td>usb_controller/game_u_s0/Q</td>
<td>sd_loader/debounce_11_s0/D</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.024</td>
<td>8.041</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>6</td>
<td>-4.758</td>
<td>usb_controller/game_u_s0/Q</td>
<td>sd_loader/debounce_22_s0/D</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.028</td>
<td>7.965</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>7</td>
<td>-4.747</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_op_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.041</td>
<td>7.694</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>8</td>
<td>-4.588</td>
<td>usb_controller/game_u_s0/Q</td>
<td>sd_loader/debounce_6_s0/D</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.036</td>
<td>7.788</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>9</td>
<td>-4.496</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/overlay_s0/D</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.028</td>
<td>7.702</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>10</td>
<td>-4.422</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_loading_s2/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.039</td>
<td>7.370</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>11</td>
<td>-4.390</td>
<td>usb_controller/game_u_s0/Q</td>
<td>sd_loader/debounce_8_s0/D</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.039</td>
<td>7.585</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>12</td>
<td>-4.381</td>
<td>usb_controller/game_u_s0/Q</td>
<td>sd_loader/debounce_14_s0/D</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.021</td>
<td>7.595</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>13</td>
<td>-4.237</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_1_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.030</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>14</td>
<td>-4.237</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_2_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.030</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>15</td>
<td>-4.237</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_3_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.030</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>16</td>
<td>-4.237</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_4_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.030</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>17</td>
<td>-4.237</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_5_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.030</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>18</td>
<td>-4.237</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_6_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.030</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>19</td>
<td>-4.228</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_7_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.021</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>20</td>
<td>-4.228</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_8_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.021</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>21</td>
<td>-4.228</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_9_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.021</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>22</td>
<td>-4.228</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_10_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.021</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>23</td>
<td>-4.228</td>
<td>usb_controller/game_a_s0/Q</td>
<td>sd_loader/sd_file_11_s0/CE</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.021</td>
<td>7.194</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>24</td>
<td>-4.148</td>
<td>usb_controller/game_u_s0/Q</td>
<td>sd_loader/pad_2_s0/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.030</td>
<td>7.044</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>25</td>
<td>-4.136</td>
<td>usb_controller/game_u_s0/Q</td>
<td>sd_loader/debounce_9_s0/D</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>3.333</td>
<td>0.039</td>
<td>7.331</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-1.797</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s/DI[3]</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s/DI[3]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.699</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-1.797</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s/DI[2]</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s/DI[2]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.699</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-1.792</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s/DI[3]</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s/DI[3]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.694</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-1.792</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s/DI[2]</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s/DI[2]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.694</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-1.725</td>
<td>controller/W_rxd_mask_s0/CE</td>
<td>controller/W_rxd_mask_s0/CE</td>
<td>clk_sdram:[R]</td>
<td>controller/W_scan_seq_pls:[R]</td>
<td>0.000</td>
<td>-1.963</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>6</td>
<td>-1.721</td>
<td>nes/multi_mapper/mmc5/expansion_ram_expansion_ram_0_0_s/CEB</td>
<td>nes/multi_mapper/mmc5/expansion_ram_expansion_ram_0_0_s/CEB</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.674</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>7</td>
<td>-1.721</td>
<td>nes/ppu/sprite_ram/oam_oam_0_0_s/CEB</td>
<td>nes/ppu/sprite_ram/oam_oam_0_0_s/CEB</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.674</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>8</td>
<td>-1.721</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s/CE</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s/CE</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.674</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>9</td>
<td>-1.716</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s0/CE</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s0/CE</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.669</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>10</td>
<td>-1.713</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s0/CE</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s0/CE</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>-0.000</td>
<td>-1.667</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>11</td>
<td>-1.713</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s/CE</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s/CE</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>-0.000</td>
<td>-1.667</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>12</td>
<td>-1.711</td>
<td>sd_loader/menu_color_4_s206/CE</td>
<td>sd_loader/menu_color_4_s206/CE</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.664</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>13</td>
<td>-1.711</td>
<td>sd_loader/menu_color_4_s205/CE</td>
<td>sd_loader/menu_color_4_s205/CE</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.664</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>14</td>
<td>-1.707</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s/AD[12]</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s/AD[12]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.674</td>
<td>0.120</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>15</td>
<td>-1.675</td>
<td>nes/multi_mapper/map69/chr_bank[0]_chr_bank[0]_0_0_s/WAD[3]</td>
<td>nes/multi_mapper/map69/chr_bank[0]_chr_bank[0]_0_0_s/WAD[3]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.697</td>
<td>0.120</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>16</td>
<td>-1.666</td>
<td>usb_controller/dat[0]_dat[0]_0_0_s/WAD[3]</td>
<td>usb_controller/dat[0]_dat[0]_0_0_s/WAD[3]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>-0.000</td>
<td>-1.689</td>
<td>0.120</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>17</td>
<td>-1.664</td>
<td>controller/W_rxd_mask_s0/RESET</td>
<td>controller/W_rxd_mask_s0/RESET</td>
<td>clk_sdram:[R]</td>
<td>controller/W_scan_seq_pls:[R]</td>
<td>0.000</td>
<td>-1.963</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>18</td>
<td>-1.661</td>
<td>usb_controller/dat[0]_dat[0]_0_1_s/WAD[3]</td>
<td>usb_controller/dat[0]_dat[0]_0_1_s/WAD[3]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>-0.000</td>
<td>-1.696</td>
<td>0.132</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>19</td>
<td>-1.636</td>
<td>usb_controller2/dat[0]_dat[0]_0_1_s/WAD[3]</td>
<td>usb_controller2/dat[0]_dat[0]_0_1_s/WAD[3]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>-0.000</td>
<td>-1.659</td>
<td>0.120</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>20</td>
<td>-1.602</td>
<td>nes/cpu/micro2/B_B_0_0_s/AD[13]</td>
<td>nes/cpu/micro2/B_B_0_0_s/AD[13]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.669</td>
<td>0.220</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>21</td>
<td>-1.599</td>
<td>usb_controller2/ukp/n716_s/CIN</td>
<td>usb_controller2/ukp/conct_1_s0/D</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
<td>-0.000</td>
<td>-1.694</td>
<td>0.131</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>22</td>
<td>-1.599</td>
<td>u_hdmi/mem_mem_3_2_s/BLKSELA[2]</td>
<td>u_hdmi/mem_mem_3_2_s/BLKSELA[2]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.674</td>
<td>0.122</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>23</td>
<td>-1.599</td>
<td>u_hdmi/mem_mem_2_5_s/BLKSELA[2]</td>
<td>u_hdmi/mem_mem_2_5_s/BLKSELA[2]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.674</td>
<td>0.122</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>24</td>
<td>-1.599</td>
<td>u_hdmi/mem_mem_2_4_s/BLKSELA[2]</td>
<td>u_hdmi/mem_mem_2_4_s/BLKSELA[2]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.674</td>
<td>0.122</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>25</td>
<td>-1.599</td>
<td>u_hdmi/mem_mem_1_4_s/BLKSELA[2]</td>
<td>u_hdmi/mem_mem_1_4_s/BLKSELA[2]</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.674</td>
<td>0.122</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-4.081</td>
<td>sys_resetn_s0/Q</td>
<td>clk_div/clkdiv_inst/RESETN</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[R]</td>
<td>2.667</td>
<td>0.908</td>
<td>5.775</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-2.510</td>
<td>sys_resetn_s0/Q</td>
<td>u_hdmi/hdmi/serializer/gwSer2/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[F]</td>
<td>1.333</td>
<td>0.908</td>
<td>2.749</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-2.510</td>
<td>sys_resetn_s0/Q</td>
<td>u_hdmi/hdmi/serializer/gwSer1/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[F]</td>
<td>1.333</td>
<td>0.908</td>
<td>2.749</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-2.510</td>
<td>sys_resetn_s0/Q</td>
<td>u_hdmi/hdmi/serializer/gwSer0/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[F]</td>
<td>1.333</td>
<td>0.908</td>
<td>2.749</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-1.179</td>
<td>sys_resetn_s0/Q</td>
<td>u_hdmi/hdmi/serializer/gwSer2/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[R]</td>
<td>2.667</td>
<td>0.908</td>
<td>2.749</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>6</td>
<td>-1.179</td>
<td>sys_resetn_s0/Q</td>
<td>u_hdmi/hdmi/serializer/gwSer1/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[R]</td>
<td>2.667</td>
<td>0.908</td>
<td>2.749</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>7</td>
<td>-1.179</td>
<td>sys_resetn_s0/Q</td>
<td>u_hdmi/hdmi/serializer/gwSer0/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[R]</td>
<td>2.667</td>
<td>0.908</td>
<td>2.749</td>
</tr>
<tr>
<td>8</td>
<td>21.643</td>
<td>memory/u_sdram/SDRAM_nWE_s0/CLEAR</td>
<td>memory/u_sdram/SDRAM_nWE_s0/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.218</td>
<td>0.192</td>
</tr>
<tr>
<td>9</td>
<td>21.756</td>
<td>nes/ppu/sprite_ram/oam_8708_REDUCAREG_G_s/CLEAR</td>
<td>nes/ppu/sprite_ram/oam_8708_REDUCAREG_G_s/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.139</td>
<td>0.000</td>
</tr>
<tr>
<td>10</td>
<td>21.772</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_0_s/CLEAR</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_0_s/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.154</td>
<td>0.000</td>
</tr>
<tr>
<td>11</td>
<td>21.774</td>
<td>uart_demux/uart/r_Clock_Count_0_s3/CLEAR</td>
<td>uart_demux/uart/r_Clock_Count_0_s3/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.157</td>
<td>0.000</td>
</tr>
<tr>
<td>12</td>
<td>21.778</td>
<td>sd_loader/menu_color_4_s38/CLEAR</td>
<td>sd_loader/menu_color_4_s38/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.160</td>
<td>0.000</td>
</tr>
<tr>
<td>13</td>
<td>21.778</td>
<td>sd_loader/menu_color_4_s29/CLEAR</td>
<td>sd_loader/menu_color_4_s29/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.160</td>
<td>0.000</td>
</tr>
<tr>
<td>14</td>
<td>21.778</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_7_s/CLEAR</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_7_s/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.160</td>
<td>0.000</td>
</tr>
<tr>
<td>15</td>
<td>21.778</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_6_s/CLEAR</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_6_s/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.160</td>
<td>0.000</td>
</tr>
<tr>
<td>16</td>
<td>21.778</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_1_s/CLEAR</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_1_s/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.160</td>
<td>0.000</td>
</tr>
<tr>
<td>17</td>
<td>21.782</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s/CLEAR</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.165</td>
<td>0.000</td>
</tr>
<tr>
<td>18</td>
<td>21.784</td>
<td>sd_loader/menu_color_4_s14/CLEAR</td>
<td>sd_loader/menu_color_4_s14/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.166</td>
<td>0.000</td>
</tr>
<tr>
<td>19</td>
<td>21.784</td>
<td>sd_loader/menu_color_4_s10/CLEAR</td>
<td>sd_loader/menu_color_4_s10/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.166</td>
<td>0.000</td>
</tr>
<tr>
<td>20</td>
<td>21.784</td>
<td>sd_loader/menu_color_4_s6/CLEAR</td>
<td>sd_loader/menu_color_4_s6/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.166</td>
<td>0.000</td>
</tr>
<tr>
<td>21</td>
<td>21.784</td>
<td>sd_loader/menu_color_4_s4/CLEAR</td>
<td>sd_loader/menu_color_4_s4/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.166</td>
<td>0.000</td>
</tr>
<tr>
<td>22</td>
<td>21.784</td>
<td>sd_loader/menu_color_4_s2/CLEAR</td>
<td>sd_loader/menu_color_4_s2/CLEAR</td>
<td>clk_sdram:[F]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>20.000</td>
<td>-2.166</td>
<td>0.000</td>
</tr>
<tr>
<td>23</td>
<td>35.763</td>
<td>sys_resetn_s0/Q</td>
<td>u_hdmi/hdmi/serializer/gwSer0/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>clk_sdram:[R]</td>
<td>40.000</td>
<td>1.300</td>
<td>2.749</td>
</tr>
<tr>
<td>24</td>
<td>35.772</td>
<td>sys_resetn_s0/Q</td>
<td>u_hdmi/hdmi/serializer/gwSer2/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>clk_sdram:[R]</td>
<td>40.000</td>
<td>1.291</td>
<td>2.749</td>
</tr>
<tr>
<td>25</td>
<td>35.772</td>
<td>sys_resetn_s0/Q</td>
<td>u_hdmi/hdmi/serializer/gwSer1/RESET</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>clk_sdram:[R]</td>
<td>40.000</td>
<td>1.291</td>
<td>2.749</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-1.548</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s1/CLEAR</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s1/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.702</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-1.543</td>
<td>spin_state_s2/CLEAR</td>
<td>spin_state_s2/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.697</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-1.541</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s/CLEAR</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.694</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-1.522</td>
<td>memory/u_sdram/cycle_0_s0/CLEAR</td>
<td>memory/u_sdram/cycle_0_s0/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.675</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-1.521</td>
<td>sd_loader/menu_color_4_s25/CLEAR</td>
<td>sd_loader/menu_color_4_s25/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.675</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>6</td>
<td>-1.519</td>
<td>sd_loader/active_2_s1/CLEAR</td>
<td>sd_loader/active_2_s1/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.673</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>7</td>
<td>-1.519</td>
<td>state_1_0_s0/CLEAR</td>
<td>state_1_0_s0/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.673</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>8</td>
<td>-1.519</td>
<td>state_0_0_s0/CLEAR</td>
<td>state_0_0_s0/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.673</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>9</td>
<td>-1.518</td>
<td>sd_loader/menu_color_4_s8/CLEAR</td>
<td>sd_loader/menu_color_4_s8/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.672</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>10</td>
<td>-1.517</td>
<td>memory/u_sdram/cycle_3_s0/CLEAR</td>
<td>memory/u_sdram/cycle_3_s0/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.670</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>11</td>
<td>-1.517</td>
<td>memory/u_sdram/cycle_1_s0/CLEAR</td>
<td>memory/u_sdram/cycle_1_s0/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.670</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>12</td>
<td>-1.517</td>
<td>memory/u_sdram/cycle_2_s0/CLEAR</td>
<td>memory/u_sdram/cycle_2_s0/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.670</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>13</td>
<td>-1.514</td>
<td>sd_loader/menu_color_4_s39/CLEAR</td>
<td>sd_loader/menu_color_4_s39/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.668</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>14</td>
<td>-1.514</td>
<td>sd_loader/menu_color_4_s27/CLEAR</td>
<td>sd_loader/menu_color_4_s27/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.668</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>15</td>
<td>-1.514</td>
<td>print_buffer_906_s1/CLEAR</td>
<td>print_buffer_906_s1/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.668</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>16</td>
<td>-1.514</td>
<td>print_buffer_866_s1/CLEAR</td>
<td>print_buffer_866_s1/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.668</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>17</td>
<td>-1.514</td>
<td>memory/u_sdram/rst_done_p1_s0/CLEAR</td>
<td>memory/u_sdram/rst_done_p1_s0/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.668</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>18</td>
<td>-1.513</td>
<td>sd_loader/menu_color_4_s14/CLEAR</td>
<td>sd_loader/menu_color_4_s14/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.667</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>19</td>
<td>-1.513</td>
<td>sd_loader/menu_color_4_s10/CLEAR</td>
<td>sd_loader/menu_color_4_s10/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.667</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>20</td>
<td>-1.513</td>
<td>sd_loader/menu_color_4_s6/CLEAR</td>
<td>sd_loader/menu_color_4_s6/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.667</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>21</td>
<td>-1.513</td>
<td>sd_loader/menu_color_4_s4/CLEAR</td>
<td>sd_loader/menu_color_4_s4/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.667</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>22</td>
<td>-1.513</td>
<td>sd_loader/menu_color_4_s2/CLEAR</td>
<td>sd_loader/menu_color_4_s2/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.667</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>23</td>
<td>-1.513</td>
<td>uart_demux/state_0_s1/CLEAR</td>
<td>uart_demux/state_0_s1/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.667</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>24</td>
<td>-1.509</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s/CLEAR</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.663</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>25</td>
<td>-1.508</td>
<td>sd_loader/menu_color_4_s38/CLEAR</td>
<td>sd_loader/menu_color_4_s38/CLEAR</td>
<td>clk_sdram:[R]</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.662</td>
<td>0.000</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>3.302</td>
<td>3.552</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>controller/W_scan_seq_pls</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
<tr>
<td>2</td>
<td>3.794</td>
<td>4.044</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>controller2/n50_15</td>
<td>controller2/rxd/O_RXD_DAT_2_s0</td>
</tr>
<tr>
<td>3</td>
<td>3.796</td>
<td>4.046</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>controller2/n50_15</td>
<td>controller2/O_RXD_1_7_s1</td>
</tr>
<tr>
<td>4</td>
<td>3.796</td>
<td>4.046</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>controller2/n50_15</td>
<td>controller2/O_RXD_1_6_s1</td>
</tr>
<tr>
<td>5</td>
<td>3.796</td>
<td>4.046</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>controller2/n50_15</td>
<td>controller2/O_RXD_2_6_s1</td>
</tr>
<tr>
<td>6</td>
<td>3.796</td>
<td>4.046</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>controller2/n50_15</td>
<td>controller2/O_RXD_2_5_s1</td>
</tr>
<tr>
<td>7</td>
<td>3.796</td>
<td>4.046</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>controller2/n50_15</td>
<td>controller2/rxd/O_RXD_DAT_7_s0</td>
</tr>
<tr>
<td>8</td>
<td>3.796</td>
<td>4.046</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>controller2/n50_15</td>
<td>controller2/rxd/O_RXD_DAT_6_s0</td>
</tr>
<tr>
<td>9</td>
<td>3.796</td>
<td>4.046</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>controller2/n50_15</td>
<td>controller2/rxd/O_RXD_DAT_3_s0</td>
</tr>
<tr>
<td>10</td>
<td>3.798</td>
<td>4.048</td>
<td>0.250</td>
<td>High Pulse Width</td>
<td>controller2/n50_15</td>
<td>controller2/rxd/O_RXD_DAT_5_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.066</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.888</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.822</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/state_1_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.945</td>
<td>3.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[0][B]</td>
<td>sd_loader/n2949_s1/I1</td>
</tr>
<tr>
<td>925.406</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R34C80[0][B]</td>
<td style=" background: #97FFFF;">sd_loader/n2949_s1/F</td>
</tr>
<tr>
<td>925.549</td>
<td>0.142</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[2][B]</td>
<td>sd_loader/state_2_s3/I0</td>
</tr>
<tr>
<td>926.075</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R34C80[2][B]</td>
<td style=" background: #97FFFF;">sd_loader/state_2_s3/F</td>
</tr>
<tr>
<td>926.888</td>
<td>0.813</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C81[2][A]</td>
<td style=" font-weight:bold;">sd_loader/state_1_s2/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.168</td>
<td>0.870</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C81[2][A]</td>
<td>sd_loader/state_1_s2/CLK</td>
</tr>
<tr>
<td>922.133</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/state_1_s2</td>
</tr>
<tr>
<td>921.822</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C81[2][A]</td>
<td>sd_loader/state_1_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.028</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.250, 15.576%; route: 6.392, 79.657%; tC2Q: 0.382, 4.766%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.870, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.960</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>927.033</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>922.073</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_u_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td>usb_controller/game_u_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td style=" font-weight:bold;">usb_controller/game_u_s0/Q</td>
</tr>
<tr>
<td>920.130</td>
<td>0.885</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][A]</td>
<td>n262_s1/I0</td>
</tr>
<tr>
<td>920.646</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R11C45[0][A]</td>
<td style=" background: #97FFFF;">n262_s1/F</td>
</tr>
<tr>
<td>924.786</td>
<td>4.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[1][B]</td>
<td>sd_loader/n3161_s2/I1</td>
</tr>
<tr>
<td>925.248</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R33C77[1][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3161_s2/F</td>
</tr>
<tr>
<td>925.253</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[0][A]</td>
<td>sd_loader/n2538_s2/I2</td>
</tr>
<tr>
<td>925.769</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R33C77[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>926.506</td>
<td>0.737</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C77[1][A]</td>
<td>sd_loader/n2526_s1/I0</td>
</tr>
<tr>
<td>927.033</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R36C77[1][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2526_s1/F</td>
</tr>
<tr>
<td>927.033</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C77[1][A]</td>
<td style=" font-weight:bold;">sd_loader/debounce_18_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.172</td>
<td>0.874</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C77[1][A]</td>
<td>sd_loader/debounce_18_s0/CLK</td>
</tr>
<tr>
<td>922.137</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/debounce_18_s0</td>
</tr>
<tr>
<td>922.073</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R36C77[1][A]</td>
<td>sd_loader/debounce_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.024</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.020, 24.725%; route: 5.767, 70.594%; tC2Q: 0.382, 4.682%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.874, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.885</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.698</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.812</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/state_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.945</td>
<td>3.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[0][B]</td>
<td>sd_loader/n2949_s1/I1</td>
</tr>
<tr>
<td>925.406</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R34C80[0][B]</td>
<td style=" background: #97FFFF;">sd_loader/n2949_s1/F</td>
</tr>
<tr>
<td>925.549</td>
<td>0.142</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[2][B]</td>
<td>sd_loader/state_2_s3/I0</td>
</tr>
<tr>
<td>926.075</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R34C80[2][B]</td>
<td style=" background: #97FFFF;">sd_loader/state_2_s3/F</td>
</tr>
<tr>
<td>926.698</td>
<td>0.623</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[1][A]</td>
<td style=" font-weight:bold;">sd_loader/state_0_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.159</td>
<td>0.861</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[1][A]</td>
<td>sd_loader/state_0_s1/CLK</td>
</tr>
<tr>
<td>922.124</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/state_0_s1</td>
</tr>
<tr>
<td>921.812</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C80[1][A]</td>
<td>sd_loader/state_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.038</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.250, 15.954%; route: 6.202, 79.164%; tC2Q: 0.382, 4.882%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.861, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.885</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.698</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.812</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/state_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.945</td>
<td>3.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[0][B]</td>
<td>sd_loader/n2949_s1/I1</td>
</tr>
<tr>
<td>925.406</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R34C80[0][B]</td>
<td style=" background: #97FFFF;">sd_loader/n2949_s1/F</td>
</tr>
<tr>
<td>925.549</td>
<td>0.142</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[2][B]</td>
<td>sd_loader/state_2_s3/I0</td>
</tr>
<tr>
<td>926.075</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R34C80[2][B]</td>
<td style=" background: #97FFFF;">sd_loader/state_2_s3/F</td>
</tr>
<tr>
<td>926.698</td>
<td>0.623</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[1][B]</td>
<td style=" font-weight:bold;">sd_loader/state_2_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.159</td>
<td>0.861</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[1][B]</td>
<td>sd_loader/state_2_s1/CLK</td>
</tr>
<tr>
<td>922.124</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/state_2_s1</td>
</tr>
<tr>
<td>921.812</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C80[1][B]</td>
<td>sd_loader/state_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.038</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.250, 15.954%; route: 6.202, 79.164%; tC2Q: 0.382, 4.882%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.861, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.831</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.904</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>922.073</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_u_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td>usb_controller/game_u_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td style=" font-weight:bold;">usb_controller/game_u_s0/Q</td>
</tr>
<tr>
<td>920.130</td>
<td>0.885</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][A]</td>
<td>n262_s1/I0</td>
</tr>
<tr>
<td>920.646</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R11C45[0][A]</td>
<td style=" background: #97FFFF;">n262_s1/F</td>
</tr>
<tr>
<td>924.786</td>
<td>4.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[1][B]</td>
<td>sd_loader/n3161_s2/I1</td>
</tr>
<tr>
<td>925.248</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R33C77[1][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3161_s2/F</td>
</tr>
<tr>
<td>925.253</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[0][A]</td>
<td>sd_loader/n2538_s2/I2</td>
</tr>
<tr>
<td>925.769</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R33C77[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>926.641</td>
<td>0.872</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C77[2][A]</td>
<td>sd_loader/n2533_s1/I0</td>
</tr>
<tr>
<td>926.904</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R36C77[2][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2533_s1/F</td>
</tr>
<tr>
<td>926.904</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C77[2][A]</td>
<td style=" font-weight:bold;">sd_loader/debounce_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.172</td>
<td>0.874</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R36C77[2][A]</td>
<td>sd_loader/debounce_11_s0/CLK</td>
</tr>
<tr>
<td>922.137</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/debounce_11_s0</td>
</tr>
<tr>
<td>922.073</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R36C77[2][A]</td>
<td>sd_loader/debounce_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.024</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.756, 21.841%; route: 5.903, 73.403%; tC2Q: 0.382, 4.757%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.874, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.758</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.828</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>922.069</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_u_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td>usb_controller/game_u_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td style=" font-weight:bold;">usb_controller/game_u_s0/Q</td>
</tr>
<tr>
<td>920.130</td>
<td>0.885</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][A]</td>
<td>n262_s1/I0</td>
</tr>
<tr>
<td>920.646</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R11C45[0][A]</td>
<td style=" background: #97FFFF;">n262_s1/F</td>
</tr>
<tr>
<td>924.786</td>
<td>4.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[1][B]</td>
<td>sd_loader/n3161_s2/I1</td>
</tr>
<tr>
<td>925.248</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R33C77[1][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3161_s2/F</td>
</tr>
<tr>
<td>925.253</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[0][A]</td>
<td>sd_loader/n2538_s2/I2</td>
</tr>
<tr>
<td>925.769</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R33C77[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>926.311</td>
<td>0.543</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C79[2][A]</td>
<td>sd_loader/n2522_s1/I3</td>
</tr>
<tr>
<td>926.828</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R34C79[2][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2522_s1/F</td>
</tr>
<tr>
<td>926.828</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C79[2][A]</td>
<td style=" font-weight:bold;">sd_loader/debounce_22_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.168</td>
<td>0.870</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C79[2][A]</td>
<td>sd_loader/debounce_22_s0/CLK</td>
</tr>
<tr>
<td>922.133</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/debounce_22_s0</td>
</tr>
<tr>
<td>922.069</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C79[2][A]</td>
<td>sd_loader/debounce_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.028</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.010, 25.235%; route: 5.573, 69.962%; tC2Q: 0.382, 4.802%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.870, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.747</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.556</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.809</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_op_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.945</td>
<td>3.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[0][B]</td>
<td>sd_loader/n2949_s1/I1</td>
</tr>
<tr>
<td>925.406</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R34C80[0][B]</td>
<td style=" background: #97FFFF;">sd_loader/n2949_s1/F</td>
</tr>
<tr>
<td>926.556</td>
<td>1.150</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C64[0][A]</td>
<td style=" font-weight:bold;">sd_loader/sd_op_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.155</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C64[0][A]</td>
<td>sd_loader/sd_op_s0/CLK</td>
</tr>
<tr>
<td>922.120</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_op_s0</td>
</tr>
<tr>
<td>921.809</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C64[0][A]</td>
<td>sd_loader/sd_op_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.041</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.724, 9.407%; route: 6.588, 85.621%; tC2Q: 0.382, 4.972%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.857, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.588</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.650</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>922.062</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_u_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td>usb_controller/game_u_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td style=" font-weight:bold;">usb_controller/game_u_s0/Q</td>
</tr>
<tr>
<td>920.130</td>
<td>0.885</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][A]</td>
<td>n262_s1/I0</td>
</tr>
<tr>
<td>920.646</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R11C45[0][A]</td>
<td style=" background: #97FFFF;">n262_s1/F</td>
</tr>
<tr>
<td>924.786</td>
<td>4.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[1][B]</td>
<td>sd_loader/n3161_s2/I1</td>
</tr>
<tr>
<td>925.248</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R33C77[1][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3161_s2/F</td>
</tr>
<tr>
<td>925.253</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[0][A]</td>
<td>sd_loader/n2538_s2/I2</td>
</tr>
<tr>
<td>925.769</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R33C77[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>926.124</td>
<td>0.355</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C76[0][A]</td>
<td>sd_loader/n2538_s1/I0</td>
</tr>
<tr>
<td>926.650</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R35C76[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2538_s1/F</td>
</tr>
<tr>
<td>926.650</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C76[0][A]</td>
<td style=" font-weight:bold;">sd_loader/debounce_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.160</td>
<td>0.862</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C76[0][A]</td>
<td>sd_loader/debounce_6_s0/CLK</td>
</tr>
<tr>
<td>922.125</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/debounce_6_s0</td>
</tr>
<tr>
<td>922.062</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C76[0][A]</td>
<td>sd_loader/debounce_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.036</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.020, 25.939%; route: 5.385, 69.149%; tC2Q: 0.382, 4.912%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.862, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.496</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.565</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>922.069</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/overlay_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.945</td>
<td>3.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[0][A]</td>
<td>sd_loader/n3073_s1/I1</td>
</tr>
<tr>
<td>925.471</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R34C80[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s1/F</td>
</tr>
<tr>
<td>926.049</td>
<td>0.577</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C75[1][A]</td>
<td>sd_loader/n2079_s5/I1</td>
</tr>
<tr>
<td>926.565</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R34C75[1][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2079_s5/F</td>
</tr>
<tr>
<td>926.565</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C75[1][A]</td>
<td style=" font-weight:bold;">sd_loader/overlay_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.168</td>
<td>0.870</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C75[1][A]</td>
<td>sd_loader/overlay_s0/CLK</td>
</tr>
<tr>
<td>922.133</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/overlay_s0</td>
</tr>
<tr>
<td>922.069</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C75[1][A]</td>
<td>sd_loader/overlay_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.028</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.305, 16.943%; route: 6.015, 78.092%; tC2Q: 0.382, 4.966%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.870, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.233</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.811</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_loading_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.945</td>
<td>3.655</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C80[0][A]</td>
<td>sd_loader/n3073_s1/I1</td>
</tr>
<tr>
<td>925.471</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R34C80[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s1/F</td>
</tr>
<tr>
<td>925.634</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C80[0][B]</td>
<td>sd_loader/sd_loading_s4/I0</td>
</tr>
<tr>
<td>926.095</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R33C80[0][B]</td>
<td style=" background: #97FFFF;">sd_loader/sd_loading_s4/F</td>
</tr>
<tr>
<td>926.233</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C80[0][A]</td>
<td style=" font-weight:bold;">sd_loader/sd_loading_s2/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.157</td>
<td>0.859</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C80[0][A]</td>
<td>sd_loader/sd_loading_s2/CLK</td>
</tr>
<tr>
<td>922.122</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_loading_s2</td>
</tr>
<tr>
<td>921.810</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C80[0][A]</td>
<td>sd_loader/sd_loading_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.039</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.250, 16.961%; route: 5.737, 77.849%; tC2Q: 0.382, 5.190%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.859, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.390</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.448</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>922.058</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_u_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td>usb_controller/game_u_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td style=" font-weight:bold;">usb_controller/game_u_s0/Q</td>
</tr>
<tr>
<td>920.130</td>
<td>0.885</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][A]</td>
<td>n262_s1/I0</td>
</tr>
<tr>
<td>920.646</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R11C45[0][A]</td>
<td style=" background: #97FFFF;">n262_s1/F</td>
</tr>
<tr>
<td>924.786</td>
<td>4.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[1][B]</td>
<td>sd_loader/n3161_s2/I1</td>
</tr>
<tr>
<td>925.248</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R33C77[1][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3161_s2/F</td>
</tr>
<tr>
<td>925.253</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[0][A]</td>
<td>sd_loader/n2538_s2/I2</td>
</tr>
<tr>
<td>925.769</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R33C77[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>925.931</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C76[0][A]</td>
<td>sd_loader/n2536_s1/I0</td>
</tr>
<tr>
<td>926.448</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R33C76[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2536_s1/F</td>
</tr>
<tr>
<td>926.448</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C76[0][A]</td>
<td style=" font-weight:bold;">sd_loader/debounce_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.157</td>
<td>0.859</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C76[0][A]</td>
<td>sd_loader/debounce_8_s0/CLK</td>
</tr>
<tr>
<td>922.122</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/debounce_8_s0</td>
</tr>
<tr>
<td>922.058</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C76[0][A]</td>
<td>sd_loader/debounce_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.039</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.010, 26.500%; route: 5.193, 68.457%; tC2Q: 0.382, 5.043%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.859, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.381</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.458</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>922.077</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_u_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td>usb_controller/game_u_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td style=" font-weight:bold;">usb_controller/game_u_s0/Q</td>
</tr>
<tr>
<td>920.130</td>
<td>0.885</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][A]</td>
<td>n262_s1/I0</td>
</tr>
<tr>
<td>920.646</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R11C45[0][A]</td>
<td style=" background: #97FFFF;">n262_s1/F</td>
</tr>
<tr>
<td>924.786</td>
<td>4.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[1][B]</td>
<td>sd_loader/n3161_s2/I1</td>
</tr>
<tr>
<td>925.248</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R33C77[1][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3161_s2/F</td>
</tr>
<tr>
<td>925.253</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[0][A]</td>
<td>sd_loader/n2538_s2/I2</td>
</tr>
<tr>
<td>925.769</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R33C77[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>925.931</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C78[2][A]</td>
<td>sd_loader/n2530_s1/I0</td>
</tr>
<tr>
<td>926.458</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R33C78[2][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2530_s1/F</td>
</tr>
<tr>
<td>926.458</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C78[2][A]</td>
<td style=" font-weight:bold;">sd_loader/debounce_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.175</td>
<td>0.877</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C78[2][A]</td>
<td>sd_loader/debounce_14_s0/CLK</td>
</tr>
<tr>
<td>922.140</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/debounce_14_s0</td>
</tr>
<tr>
<td>922.077</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C78[2][A]</td>
<td>sd_loader/debounce_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.020, 26.596%; route: 5.193, 68.367%; tC2Q: 0.382, 5.036%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.877, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.237</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.820</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[0][A]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[0][A]</td>
<td>sd_loader/sd_file_1_s0/CLK</td>
</tr>
<tr>
<td>922.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_1_s0</td>
</tr>
<tr>
<td>921.820</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C65[0][A]</td>
<td>sd_loader/sd_file_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.030</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.237</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.820</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[0][B]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_2_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[0][B]</td>
<td>sd_loader/sd_file_2_s0/CLK</td>
</tr>
<tr>
<td>922.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_2_s0</td>
</tr>
<tr>
<td>921.820</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C65[0][B]</td>
<td>sd_loader/sd_file_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.030</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.237</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.820</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[1][A]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_3_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[1][A]</td>
<td>sd_loader/sd_file_3_s0/CLK</td>
</tr>
<tr>
<td>922.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_3_s0</td>
</tr>
<tr>
<td>921.820</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C65[1][A]</td>
<td>sd_loader/sd_file_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.030</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.237</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.820</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[1][B]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_4_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[1][B]</td>
<td>sd_loader/sd_file_4_s0/CLK</td>
</tr>
<tr>
<td>922.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_4_s0</td>
</tr>
<tr>
<td>921.820</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C65[1][B]</td>
<td>sd_loader/sd_file_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.030</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.237</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.820</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[2][A]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_5_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[2][A]</td>
<td>sd_loader/sd_file_5_s0/CLK</td>
</tr>
<tr>
<td>922.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_5_s0</td>
</tr>
<tr>
<td>921.820</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C65[2][A]</td>
<td>sd_loader/sd_file_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.030</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.237</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.820</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[2][B]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_6_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C65[2][B]</td>
<td>sd_loader/sd_file_6_s0/CLK</td>
</tr>
<tr>
<td>922.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_6_s0</td>
</tr>
<tr>
<td>921.820</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C65[2][B]</td>
<td>sd_loader/sd_file_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.030</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.228</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.829</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[0][A]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_7_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.175</td>
<td>0.877</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[0][A]</td>
<td>sd_loader/sd_file_7_s0/CLK</td>
</tr>
<tr>
<td>922.140</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_7_s0</td>
</tr>
<tr>
<td>921.829</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C66[0][A]</td>
<td>sd_loader/sd_file_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.877, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.228</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.829</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[0][B]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_8_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.175</td>
<td>0.877</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[0][B]</td>
<td>sd_loader/sd_file_8_s0/CLK</td>
</tr>
<tr>
<td>922.140</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_8_s0</td>
</tr>
<tr>
<td>921.829</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C66[0][B]</td>
<td>sd_loader/sd_file_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.877, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.228</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.829</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[1][A]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_9_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.175</td>
<td>0.877</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[1][A]</td>
<td>sd_loader/sd_file_9_s0/CLK</td>
</tr>
<tr>
<td>922.140</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_9_s0</td>
</tr>
<tr>
<td>921.829</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C66[1][A]</td>
<td>sd_loader/sd_file_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.877, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.228</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.829</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[1][B]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_10_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.175</td>
<td>0.877</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[1][B]</td>
<td>sd_loader/sd_file_10_s0/CLK</td>
</tr>
<tr>
<td>922.140</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_10_s0</td>
</tr>
<tr>
<td>921.829</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C66[1][B]</td>
<td>sd_loader/sd_file_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.877, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.228</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.829</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_a_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/sd_file_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td>usb_controller/game_a_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C41[0][B]</td>
<td style=" font-weight:bold;">usb_controller/game_a_s0/Q</td>
</tr>
<tr>
<td>921.028</td>
<td>1.782</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>n266_s1/I1</td>
</tr>
<tr>
<td>921.290</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">n266_s1/F</td>
</tr>
<tr>
<td>924.615</td>
<td>3.325</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C76[3][B]</td>
<td>sd_loader/n3073_s2/I1</td>
</tr>
<tr>
<td>924.880</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R34C76[3][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3073_s2/F</td>
</tr>
<tr>
<td>926.057</td>
<td>1.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[2][A]</td>
<td style=" font-weight:bold;">sd_loader/sd_file_11_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.175</td>
<td>0.877</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C66[2][A]</td>
<td>sd_loader/sd_file_11_s0/CLK</td>
</tr>
<tr>
<td>922.140</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/sd_file_11_s0</td>
</tr>
<tr>
<td>921.829</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C66[2][A]</td>
<td>sd_loader/sd_file_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.021</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.527, 7.332%; route: 6.284, 87.351%; tC2Q: 0.382, 5.317%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.877, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.148</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>925.906</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>921.759</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_u_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/pad_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td>usb_controller/game_u_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td style=" font-weight:bold;">usb_controller/game_u_s0/Q</td>
</tr>
<tr>
<td>920.130</td>
<td>0.885</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][A]</td>
<td>n262_s1/I0</td>
</tr>
<tr>
<td>920.646</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R11C45[0][A]</td>
<td style=" background: #97FFFF;">n262_s1/F</td>
</tr>
<tr>
<td>924.786</td>
<td>4.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[0][B]</td>
<td>sd_loader/n3161_s3/I1</td>
</tr>
<tr>
<td>925.248</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R33C77[0][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3161_s3/F</td>
</tr>
<tr>
<td>925.253</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[2][B]</td>
<td>sd_loader/n3160_s1/I1</td>
</tr>
<tr>
<td>925.769</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R33C77[2][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3160_s1/F</td>
</tr>
<tr>
<td>925.906</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[1][A]</td>
<td style=" font-weight:bold;">sd_loader/pad_2_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[1][A]</td>
<td>sd_loader/pad_2_s0/CLK</td>
</tr>
<tr>
<td>922.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/pad_2_s0</td>
</tr>
<tr>
<td>921.759</td>
<td>-0.373</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C77[1][A]</td>
<td>sd_loader/pad_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.030</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.494, 21.207%; route: 5.168, 73.363%; tC2Q: 0.382, 5.430%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.136</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>926.194</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>922.058</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/game_u_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/debounce_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>916.667</td>
<td>916.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>916.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>917.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>918.863</td>
<td>0.898</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td>usb_controller/game_u_s0/CLK</td>
</tr>
<tr>
<td>919.245</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C45[1][B]</td>
<td style=" font-weight:bold;">usb_controller/game_u_s0/Q</td>
</tr>
<tr>
<td>920.130</td>
<td>0.885</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C45[0][A]</td>
<td>n262_s1/I0</td>
</tr>
<tr>
<td>920.646</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R11C45[0][A]</td>
<td style=" background: #97FFFF;">n262_s1/F</td>
</tr>
<tr>
<td>924.786</td>
<td>4.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[1][B]</td>
<td>sd_loader/n3161_s2/I1</td>
</tr>
<tr>
<td>925.248</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R33C77[1][B]</td>
<td style=" background: #97FFFF;">sd_loader/n3161_s2/F</td>
</tr>
<tr>
<td>925.253</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C77[0][A]</td>
<td>sd_loader/n2538_s2/I2</td>
</tr>
<tr>
<td>925.769</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>R33C77[0][A]</td>
<td style=" background: #97FFFF;">sd_loader/n2538_s2/F</td>
</tr>
<tr>
<td>925.931</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C76[0][B]</td>
<td>sd_loader/n2535_s1/I0</td>
</tr>
<tr>
<td>926.194</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R33C76[0][B]</td>
<td style=" background: #97FFFF;">sd_loader/n2535_s1/F</td>
</tr>
<tr>
<td>926.194</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C76[0][B]</td>
<td style=" font-weight:bold;">sd_loader/debounce_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>920.000</td>
<td>920.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>920.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>921.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>922.157</td>
<td>0.859</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C76[0][B]</td>
<td>sd_loader/debounce_9_s0/CLK</td>
</tr>
<tr>
<td>922.122</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/debounce_9_s0</td>
</tr>
<tr>
<td>922.058</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C76[0][B]</td>
<td>sd_loader/debounce_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.039</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>3.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.898, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.756, 23.956%; route: 5.193, 70.827%; tC2Q: 0.382, 5.217%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.859, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.797</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.797</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C18</td>
<td style=" font-weight:bold;">nes/ppu/palette_ram/palette_palette_1_1_s/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.699</td>
<td>0.402</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C18</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s/CLK</td>
</tr>
<tr>
<td>1.734</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s</td>
</tr>
<tr>
<td>1.797</td>
<td>0.063</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C18</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.699</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.402, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.797</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.797</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C18</td>
<td style=" font-weight:bold;">nes/ppu/palette_ram/palette_palette_1_1_s/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.699</td>
<td>0.402</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C18</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s/CLK</td>
</tr>
<tr>
<td>1.734</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s</td>
</tr>
<tr>
<td>1.797</td>
<td>0.063</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C18</td>
<td>nes/ppu/palette_ram/palette_palette_1_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.699</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.402, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.792</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.792</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C17</td>
<td style=" font-weight:bold;">nes/ppu/palette_ram/palette_palette_0_1_s/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.694</td>
<td>0.397</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C17</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s/CLK</td>
</tr>
<tr>
<td>1.729</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s</td>
</tr>
<tr>
<td>1.792</td>
<td>0.063</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C17</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.694</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.397, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.792</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.792</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C17</td>
<td style=" font-weight:bold;">nes/ppu/palette_ram/palette_palette_0_1_s/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.694</td>
<td>0.397</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C17</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s/CLK</td>
</tr>
<tr>
<td>1.729</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s</td>
</tr>
<tr>
<td>1.792</td>
<td>0.063</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C17</td>
<td>nes/ppu/palette_ram/palette_palette_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.694</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.397, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.725</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.725</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>controller/W_scan_seq_pls:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C47[1][A]</td>
<td style=" font-weight:bold;">controller/W_rxd_mask_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>R16C48[0][B]</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>1.963</td>
<td>1.963</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C47[1][A]</td>
<td>controller/W_rxd_mask_s0/CLK</td>
</tr>
<tr>
<td>1.998</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>controller/W_rxd_mask_s0</td>
</tr>
<tr>
<td>1.725</td>
<td>-0.272</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C47[1][A]</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.963</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.963, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.721</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.721</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/multi_mapper/mmc5/expansion_ram_expansion_ram_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/multi_mapper/mmc5/expansion_ram_expansion_ram_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[4]</td>
<td style=" font-weight:bold;">nes/multi_mapper/mmc5/expansion_ram_expansion_ram_0_0_s/CEB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.674</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[4]</td>
<td>nes/multi_mapper/mmc5/expansion_ram_expansion_ram_0_0_s/CLKB</td>
</tr>
<tr>
<td>1.709</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/multi_mapper/mmc5/expansion_ram_expansion_ram_0_0_s</td>
</tr>
<tr>
<td>1.721</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[4]</td>
<td>nes/multi_mapper/mmc5/expansion_ram_expansion_ram_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.674</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.376, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.721</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.721</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/sprite_ram/oam_oam_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/sprite_ram/oam_oam_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[4]</td>
<td style=" font-weight:bold;">nes/ppu/sprite_ram/oam_oam_0_0_s/CEB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.674</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[4]</td>
<td>nes/ppu/sprite_ram/oam_oam_0_0_s/CLKB</td>
</tr>
<tr>
<td>1.709</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/sprite_ram/oam_oam_0_0_s</td>
</tr>
<tr>
<td>1.721</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[4]</td>
<td>nes/ppu/sprite_ram/oam_oam_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.674</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.376, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.721</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.721</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[8]</td>
<td style=" font-weight:bold;">nes/apu/lookup/lookup_lookup_0_0_s/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.674</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[8]</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s/CLK</td>
</tr>
<tr>
<td>1.709</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/apu/lookup/lookup_lookup_0_0_s</td>
</tr>
<tr>
<td>1.721</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[8]</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.674</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.376, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.716</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.716</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[7]</td>
<td style=" font-weight:bold;">nes/apu/lookup/lookup_lookup_0_0_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.669</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[7]</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s0/CLK</td>
</tr>
<tr>
<td>1.704</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/apu/lookup/lookup_lookup_0_0_s0</td>
</tr>
<tr>
<td>1.716</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[7]</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.669</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.371, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.713</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1000.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1001.714</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[11]</td>
<td style=" font-weight:bold;">usb_controller2/ukp/ukprom/mem_mem_0_0_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1001.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1001.667</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[11]</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s0/CLK</td>
</tr>
<tr>
<td>1001.702</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s0</td>
</tr>
<tr>
<td>1001.714</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[11]</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.667</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.369, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.713</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1000.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1001.714</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">usb_controller2/ukp/ukprom/mem_mem_0_0_s/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1001.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1001.667</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s/CLK</td>
</tr>
<tr>
<td>1001.702</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s</td>
</tr>
<tr>
<td>1001.714</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>usb_controller2/ukp/ukprom/mem_mem_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.667</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.369, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.711</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.711</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s206</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s206</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[22]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s206/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.664</td>
<td>0.366</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[22]</td>
<td>sd_loader/menu_color_4_s206/CLK</td>
</tr>
<tr>
<td>1.699</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s206</td>
</tr>
<tr>
<td>1.711</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[22]</td>
<td>sd_loader/menu_color_4_s206</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.664</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.366, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.711</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.711</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s205</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s205</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[21]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s205/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.664</td>
<td>0.366</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[21]</td>
<td>sd_loader/menu_color_4_s205/CLK</td>
</tr>
<tr>
<td>1.699</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s205</td>
</tr>
<tr>
<td>1.711</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[21]</td>
<td>sd_loader/menu_color_4_s205</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.664</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.366, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.707</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.120</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.827</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>824</td>
<td>-</td>
<td>VCC_cZ/V</td>
</tr>
<tr>
<td>0.120</td>
<td>0.120</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[8]</td>
<td style=" font-weight:bold;">nes/apu/lookup/lookup_lookup_0_0_s/AD[12]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.674</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[8]</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s/CLK</td>
</tr>
<tr>
<td>1.709</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/apu/lookup/lookup_lookup_0_0_s</td>
</tr>
<tr>
<td>1.827</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[8]</td>
<td>nes/apu/lookup/lookup_lookup_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.674</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.120, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.376, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.675</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.120</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.795</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/multi_mapper/map69/chr_bank[0]_chr_bank[0]_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/multi_mapper/map69/chr_bank[0]_chr_bank[0]_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.120</td>
<td>0.120</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C22</td>
<td style=" font-weight:bold;">nes/multi_mapper/map69/chr_bank[0]_chr_bank[0]_0_0_s/WAD[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.697</td>
<td>0.399</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C22</td>
<td>nes/multi_mapper/map69/chr_bank[0]_chr_bank[0]_0_0_s/CLK</td>
</tr>
<tr>
<td>1.732</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/multi_mapper/map69/chr_bank[0]_chr_bank[0]_0_0_s</td>
</tr>
<tr>
<td>1.795</td>
<td>0.063</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C22</td>
<td>nes/multi_mapper/map69/chr_bank[0]_chr_bank[0]_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.697</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.120, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.399, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.666</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1000.120</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1001.786</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/dat[0]_dat[0]_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>usb_controller/dat[0]_dat[0]_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>1000.120</td>
<td>0.120</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C40</td>
<td style=" font-weight:bold;">usb_controller/dat[0]_dat[0]_0_0_s/WAD[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1001.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1001.689</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C40</td>
<td>usb_controller/dat[0]_dat[0]_0_0_s/CLK</td>
</tr>
<tr>
<td>1001.724</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>usb_controller/dat[0]_dat[0]_0_0_s</td>
</tr>
<tr>
<td>1001.787</td>
<td>0.063</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C40</td>
<td>usb_controller/dat[0]_dat[0]_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.689</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.120, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.391, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.664</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.664</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>controller/W_scan_seq_pls:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C47[1][A]</td>
<td style=" font-weight:bold;">controller/W_rxd_mask_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>R16C48[0][B]</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>1.963</td>
<td>1.963</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C47[1][A]</td>
<td>controller/W_rxd_mask_s0/CLK</td>
</tr>
<tr>
<td>1.998</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>controller/W_rxd_mask_s0</td>
</tr>
<tr>
<td>1.664</td>
<td>-0.334</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C47[1][A]</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.963</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.963, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.661</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1000.133</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1001.794</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller/dat[0]_dat[0]_0_1_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>usb_controller/dat[0]_dat[0]_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>1000.133</td>
<td>0.132</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C39</td>
<td style=" font-weight:bold;">usb_controller/dat[0]_dat[0]_0_1_s/WAD[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1001.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1001.696</td>
<td>0.398</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C39</td>
<td>usb_controller/dat[0]_dat[0]_0_1_s/CLK</td>
</tr>
<tr>
<td>1001.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>usb_controller/dat[0]_dat[0]_0_1_s</td>
</tr>
<tr>
<td>1001.794</td>
<td>0.063</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R2C39</td>
<td>usb_controller/dat[0]_dat[0]_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.696</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.132, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.398, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.636</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1000.120</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1001.756</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller2/dat[0]_dat[0]_0_1_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>usb_controller2/dat[0]_dat[0]_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>1000.120</td>
<td>0.120</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C43</td>
<td style=" font-weight:bold;">usb_controller2/dat[0]_dat[0]_0_1_s/WAD[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1000.000</td>
<td>1000.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1000.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>1001.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>1001.659</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C43</td>
<td>usb_controller2/dat[0]_dat[0]_0_1_s/CLK</td>
</tr>
<tr>
<td>1001.694</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>usb_controller2/dat[0]_dat[0]_0_1_s</td>
</tr>
<tr>
<td>1001.757</td>
<td>0.063</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R14C43</td>
<td>usb_controller2/dat[0]_dat[0]_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.659</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.120, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.361, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.602</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.220</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.822</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/cpu/micro2/B_B_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/cpu/micro2/B_B_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.220</td>
<td>0.220</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[3]</td>
<td style=" font-weight:bold;">nes/cpu/micro2/B_B_0_0_s/AD[13]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.669</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[3]</td>
<td>nes/cpu/micro2/B_B_0_0_s/CLK</td>
</tr>
<tr>
<td>1.704</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/cpu/micro2/B_B_0_0_s</td>
</tr>
<tr>
<td>1.822</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[3]</td>
<td>nes/cpu/micro2/B_B_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.669</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.220, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.371, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.599</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>500.131</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>501.730</td>
</tr>
<tr>
<td class="label">From</td>
<td>usb_controller2/ukp/n716_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>usb_controller2/ukp/conct_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>500.000</td>
<td>500.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C43[0][A]</td>
<td style=" font-weight:bold;">usb_controller2/ukp/n716_s/CIN</td>
</tr>
<tr>
<td>500.131</td>
<td>0.131</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td style=" background: #97FFFF;">usb_controller2/ukp/n716_s/SUM</td>
</tr>
<tr>
<td>500.131</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td style=" font-weight:bold;">usb_controller2/ukp/conct_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>500.000</td>
<td>500.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>500.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT0.default_gen_clk</td>
</tr>
<tr>
<td>501.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>392</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT0</td>
</tr>
<tr>
<td>501.694</td>
<td>0.396</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td>usb_controller2/ukp/conct_1_s0/CLK</td>
</tr>
<tr>
<td>501.729</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>usb_controller2/ukp/conct_1_s0</td>
</tr>
<tr>
<td>501.730</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C43[0][A]</td>
<td>usb_controller2/ukp/conct_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.694</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.131, 100.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.396, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.599</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.122</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.721</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_hdmi/mem_mem_3_2_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/mem_mem_3_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.122</td>
<td>0.122</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[23]</td>
<td style=" font-weight:bold;">u_hdmi/mem_mem_3_2_s/BLKSELA[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.674</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[23]</td>
<td>u_hdmi/mem_mem_3_2_s/CLKA</td>
</tr>
<tr>
<td>1.709</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/mem_mem_3_2_s</td>
</tr>
<tr>
<td>1.721</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[23]</td>
<td>u_hdmi/mem_mem_3_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.674</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.122, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.376, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.599</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.122</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.721</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_hdmi/mem_mem_2_5_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/mem_mem_2_5_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.122</td>
<td>0.122</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[19]</td>
<td style=" font-weight:bold;">u_hdmi/mem_mem_2_5_s/BLKSELA[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.674</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[19]</td>
<td>u_hdmi/mem_mem_2_5_s/CLKA</td>
</tr>
<tr>
<td>1.709</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/mem_mem_2_5_s</td>
</tr>
<tr>
<td>1.721</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[19]</td>
<td>u_hdmi/mem_mem_2_5_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.674</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.122, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.376, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.599</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.122</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.721</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_hdmi/mem_mem_2_4_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/mem_mem_2_4_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.122</td>
<td>0.122</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[19]</td>
<td style=" font-weight:bold;">u_hdmi/mem_mem_2_4_s/BLKSELA[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.674</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[19]</td>
<td>u_hdmi/mem_mem_2_4_s/CLKA</td>
</tr>
<tr>
<td>1.709</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/mem_mem_2_4_s</td>
</tr>
<tr>
<td>1.721</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[19]</td>
<td>u_hdmi/mem_mem_2_4_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.674</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.122, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.376, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.599</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.122</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.721</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_hdmi/mem_mem_1_4_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/mem_mem_1_4_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.122</td>
<td>0.122</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td style=" font-weight:bold;">u_hdmi/mem_mem_1_4_s/BLKSELA[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.674</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>u_hdmi/mem_mem_1_4_s/CLKA</td>
</tr>
<tr>
<td>1.709</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/mem_mem_1_4_s</td>
</tr>
<tr>
<td>1.721</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[15]</td>
<td>u_hdmi/mem_mem_1_4_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.674</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.122, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.376, 100.000%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.081</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.981</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.900</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_div/clkdiv_inst</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.589</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>5.174</td>
<td>2.585</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C38[3][B]</td>
<td>n91_s0/I0</td>
</tr>
<tr>
<td>5.439</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R16C38[3][B]</td>
<td style=" background: #97FFFF;">n91_s0/F</td>
</tr>
<tr>
<td>7.981</td>
<td>2.543</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>TOPSIDE[0]</td>
<td style=" font-weight:bold;">clk_div/clkdiv_inst/RESETN</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2.667</td>
<td>2.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
</tr>
<tr>
<td>3.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT2</td>
</tr>
<tr>
<td>3.965</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>5</td>
<td>TOPSIDE[0]</td>
<td>clk_div/clkdiv_inst/HCLKIN</td>
</tr>
<tr>
<td>3.930</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_div/clkdiv_inst</td>
</tr>
<tr>
<td>3.900</td>
<td>-0.030</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>TOPSIDE[0]</td>
<td>clk_div/clkdiv_inst</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.908</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>2.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.265, 4.589%; route: 5.128, 88.788%; tC2Q: 0.382, 6.623%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.510</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.955</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.445</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/hdmi/serializer/gwSer2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.574</td>
<td>0.368</td>
<td>tC2Q</td>
<td>RF</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>4.955</td>
<td>2.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT72[A]</td>
<td style=" font-weight:bold;">u_hdmi/hdmi/serializer/gwSer2/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.333</td>
<td>1.333</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.333</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
</tr>
<tr>
<td>2.631</td>
<td>1.298</td>
<td>tCL</td>
<td>FF</td>
<td>4</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT2</td>
</tr>
<tr>
<td>2.631</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT72[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer2/FCLK</td>
</tr>
<tr>
<td>2.596</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/hdmi/serializer/gwSer2</td>
</tr>
<tr>
<td>2.445</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT72[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.908</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.382, 86.632%; tC2Q: 0.368, 13.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.510</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.955</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.445</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/hdmi/serializer/gwSer1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.574</td>
<td>0.368</td>
<td>tC2Q</td>
<td>RF</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>4.955</td>
<td>2.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT68[A]</td>
<td style=" font-weight:bold;">u_hdmi/hdmi/serializer/gwSer1/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.333</td>
<td>1.333</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.333</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
</tr>
<tr>
<td>2.631</td>
<td>1.298</td>
<td>tCL</td>
<td>FF</td>
<td>4</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT2</td>
</tr>
<tr>
<td>2.631</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT68[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer1/FCLK</td>
</tr>
<tr>
<td>2.596</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/hdmi/serializer/gwSer1</td>
</tr>
<tr>
<td>2.445</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT68[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.908</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.382, 86.632%; tC2Q: 0.368, 13.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.510</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.955</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.445</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/hdmi/serializer/gwSer0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.574</td>
<td>0.368</td>
<td>tC2Q</td>
<td>RF</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>4.955</td>
<td>2.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT66[A]</td>
<td style=" font-weight:bold;">u_hdmi/hdmi/serializer/gwSer0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>1.333</td>
<td>1.333</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>1.333</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
</tr>
<tr>
<td>2.631</td>
<td>1.298</td>
<td>tCL</td>
<td>FF</td>
<td>4</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT2</td>
</tr>
<tr>
<td>2.631</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT66[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer0/FCLK</td>
</tr>
<tr>
<td>2.596</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/hdmi/serializer/gwSer0</td>
</tr>
<tr>
<td>2.445</td>
<td>-0.151</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT66[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.908</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.333</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.382, 86.632%; tC2Q: 0.368, 13.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.179</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.955</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.777</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/hdmi/serializer/gwSer2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.574</td>
<td>0.368</td>
<td>tC2Q</td>
<td>RF</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>4.955</td>
<td>2.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT72[A]</td>
<td style=" font-weight:bold;">u_hdmi/hdmi/serializer/gwSer2/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2.667</td>
<td>2.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
</tr>
<tr>
<td>3.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT2</td>
</tr>
<tr>
<td>3.965</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT72[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer2/FCLK</td>
</tr>
<tr>
<td>3.930</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/hdmi/serializer/gwSer2</td>
</tr>
<tr>
<td>3.777</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT72[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.908</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>2.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.382, 86.632%; tC2Q: 0.368, 13.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.179</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.955</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.777</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/hdmi/serializer/gwSer1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.574</td>
<td>0.368</td>
<td>tC2Q</td>
<td>RF</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>4.955</td>
<td>2.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT68[A]</td>
<td style=" font-weight:bold;">u_hdmi/hdmi/serializer/gwSer1/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2.667</td>
<td>2.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
</tr>
<tr>
<td>3.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT2</td>
</tr>
<tr>
<td>3.965</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT68[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer1/FCLK</td>
</tr>
<tr>
<td>3.930</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/hdmi/serializer/gwSer1</td>
</tr>
<tr>
<td>3.777</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT68[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.908</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>2.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.382, 86.632%; tC2Q: 0.368, 13.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.179</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.955</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.777</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/hdmi/serializer/gwSer0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.574</td>
<td>0.368</td>
<td>tC2Q</td>
<td>RF</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>4.955</td>
<td>2.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT66[A]</td>
<td style=" font-weight:bold;">u_hdmi/hdmi/serializer/gwSer0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2.667</td>
<td>2.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT2.default_gen_clk</td>
</tr>
<tr>
<td>3.965</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>4</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT2</td>
</tr>
<tr>
<td>3.965</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT66[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer0/FCLK</td>
</tr>
<tr>
<td>3.930</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/hdmi/serializer/gwSer0</td>
</tr>
<tr>
<td>3.777</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT66[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.908</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>2.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.382, 86.632%; tC2Q: 0.368, 13.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.643</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.192</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.835</td>
</tr>
<tr>
<td class="label">From</td>
<td>memory/u_sdram/SDRAM_nWE_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>memory/u_sdram/SDRAM_nWE_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.192</td>
<td>0.192</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT21[B]</td>
<td style=" font-weight:bold;">memory/u_sdram/SDRAM_nWE_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.218</td>
<td>0.920</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT21[B]</td>
<td>memory/u_sdram/SDRAM_nWE_s0/CLK</td>
</tr>
<tr>
<td>42.183</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>memory/u_sdram/SDRAM_nWE_s0</td>
</tr>
<tr>
<td>41.835</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT21[B]</td>
<td>memory/u_sdram/SDRAM_nWE_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.218</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.192, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.920, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.756</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.756</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/sprite_ram/oam_8708_REDUCAREG_G_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/sprite_ram/oam_8708_REDUCAREG_G_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C16[0][A]</td>
<td style=" font-weight:bold;">nes/ppu/sprite_ram/oam_8708_REDUCAREG_G_s/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.139</td>
<td>0.841</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C16[0][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_REDUCAREG_G_s/CLK</td>
</tr>
<tr>
<td>42.104</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/sprite_ram/oam_8708_REDUCAREG_G_s</td>
</tr>
<tr>
<td>41.756</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C16[0][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_REDUCAREG_G_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.139</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.841, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.772</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.772</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C17[0][B]</td>
<td style=" font-weight:bold;">nes/ppu/sprite_ram/oam_8708_DIAREG_G_0_s/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.154</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C17[0][B]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_0_s/CLK</td>
</tr>
<tr>
<td>42.119</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_0_s</td>
</tr>
<tr>
<td>41.772</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C17[0][B]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.154</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.774</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.774</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_demux/uart/r_Clock_Count_0_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_demux/uart/r_Clock_Count_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C36[0][A]</td>
<td style=" font-weight:bold;">uart_demux/uart/r_Clock_Count_0_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.157</td>
<td>0.859</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C36[0][A]</td>
<td>uart_demux/uart/r_Clock_Count_0_s3/CLK</td>
</tr>
<tr>
<td>42.122</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>uart_demux/uart/r_Clock_Count_0_s3</td>
</tr>
<tr>
<td>41.774</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C36[0][A]</td>
<td>uart_demux/uart/r_Clock_Count_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.157</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.859, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.778</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s38</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s38</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R32C73[0][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s38/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.160</td>
<td>0.862</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C73[0][A]</td>
<td>sd_loader/menu_color_4_s38/CLK</td>
</tr>
<tr>
<td>42.125</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s38</td>
</tr>
<tr>
<td>41.778</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R32C73[0][A]</td>
<td>sd_loader/menu_color_4_s38</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.160</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.862, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.778</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s29</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s29</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R32C73[0][B]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s29/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.160</td>
<td>0.862</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C73[0][B]</td>
<td>sd_loader/menu_color_4_s29/CLK</td>
</tr>
<tr>
<td>42.125</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s29</td>
</tr>
<tr>
<td>41.778</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R32C73[0][B]</td>
<td>sd_loader/menu_color_4_s29</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.160</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.862, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.778</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_7_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_7_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C17[0][A]</td>
<td style=" font-weight:bold;">nes/ppu/sprite_ram/oam_8708_DIAREG_G_7_s/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.160</td>
<td>0.862</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C17[0][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_7_s/CLK</td>
</tr>
<tr>
<td>42.125</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_7_s</td>
</tr>
<tr>
<td>41.778</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R14C17[0][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_7_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.160</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.862, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.778</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_6_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_6_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C17[2][A]</td>
<td style=" font-weight:bold;">nes/ppu/sprite_ram/oam_8708_DIAREG_G_6_s/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.160</td>
<td>0.862</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C17[2][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_6_s/CLK</td>
</tr>
<tr>
<td>42.125</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_6_s</td>
</tr>
<tr>
<td>41.778</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R14C17[2][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_6_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.160</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.862, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.778</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_1_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C17[0][B]</td>
<td style=" font-weight:bold;">nes/ppu/sprite_ram/oam_8708_DIAREG_G_1_s/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.160</td>
<td>0.862</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C17[0][B]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_1_s/CLK</td>
</tr>
<tr>
<td>42.125</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_1_s</td>
</tr>
<tr>
<td>41.778</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R14C17[0][B]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.160</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.862, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.782</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.782</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C17[3][A]</td>
<td style=" font-weight:bold;">nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.165</td>
<td>0.867</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[3][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s/CLK</td>
</tr>
<tr>
<td>42.130</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s</td>
</tr>
<tr>
<td>41.782</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C17[3][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.165</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.867, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.784</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.784</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s14</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s14</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R33C75[0][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s14/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[0][A]</td>
<td>sd_loader/menu_color_4_s14/CLK</td>
</tr>
<tr>
<td>42.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s14</td>
</tr>
<tr>
<td>41.784</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C75[0][A]</td>
<td>sd_loader/menu_color_4_s14</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.166</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.784</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.784</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s10</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R33C75[0][B]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s10/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[0][B]</td>
<td>sd_loader/menu_color_4_s10/CLK</td>
</tr>
<tr>
<td>42.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s10</td>
</tr>
<tr>
<td>41.784</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C75[0][B]</td>
<td>sd_loader/menu_color_4_s10</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.166</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.784</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.784</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s6</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s6</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R33C73[3][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s6/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C73[3][A]</td>
<td>sd_loader/menu_color_4_s6/CLK</td>
</tr>
<tr>
<td>42.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s6</td>
</tr>
<tr>
<td>41.784</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C73[3][A]</td>
<td>sd_loader/menu_color_4_s6</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.166</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.784</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.784</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R33C75[1][B]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s4/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[1][B]</td>
<td>sd_loader/menu_color_4_s4/CLK</td>
</tr>
<tr>
<td>42.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s4</td>
</tr>
<tr>
<td>41.784</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C75[1][B]</td>
<td>sd_loader/menu_color_4_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.166</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>21.784</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>41.784</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R33C75[1][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s2/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>41.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>42.166</td>
<td>0.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[1][A]</td>
<td>sd_loader/menu_color_4_s2/CLK</td>
</tr>
<tr>
<td>42.131</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s2</td>
</tr>
<tr>
<td>41.784</td>
<td>-0.347</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R33C75[1][A]</td>
<td>sd_loader/menu_color_4_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.166</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.868, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>35.763</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.955</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.718</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/hdmi/serializer/gwSer0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.574</td>
<td>0.368</td>
<td>tC2Q</td>
<td>RF</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>4.955</td>
<td>2.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT66[A]</td>
<td style=" font-weight:bold;">u_hdmi/hdmi/serializer/gwSer0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>728</td>
<td>TOPSIDE[0]</td>
<td>clk_div/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.906</td>
<td>0.906</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT66[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer0/PCLK</td>
</tr>
<tr>
<td>40.871</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/hdmi/serializer/gwSer0</td>
</tr>
<tr>
<td>40.718</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT66[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.300</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>40.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.382, 86.632%; tC2Q: 0.368, 13.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.906, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>35.772</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.955</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.727</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/hdmi/serializer/gwSer2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.574</td>
<td>0.368</td>
<td>tC2Q</td>
<td>RF</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>4.955</td>
<td>2.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT72[A]</td>
<td style=" font-weight:bold;">u_hdmi/hdmi/serializer/gwSer2/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>728</td>
<td>TOPSIDE[0]</td>
<td>clk_div/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.915</td>
<td>0.915</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT72[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer2/PCLK</td>
</tr>
<tr>
<td>40.880</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/hdmi/serializer/gwSer2</td>
</tr>
<tr>
<td>40.727</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT72[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.291</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>40.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.382, 86.632%; tC2Q: 0.368, 13.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.915, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>35.772</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.955</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.727</td>
</tr>
<tr>
<td class="label">From</td>
<td>sys_resetn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/hdmi/serializer/gwSer1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>2.206</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>sys_resetn_s0/CLK</td>
</tr>
<tr>
<td>2.574</td>
<td>0.368</td>
<td>tC2Q</td>
<td>RF</td>
<td>370</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">sys_resetn_s0/Q</td>
</tr>
<tr>
<td>4.955</td>
<td>2.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT68[A]</td>
<td style=" font-weight:bold;">u_hdmi/hdmi/serializer/gwSer1/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>728</td>
<td>TOPSIDE[0]</td>
<td>clk_div/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.915</td>
<td>0.915</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT68[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer1/PCLK</td>
</tr>
<tr>
<td>40.880</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>u_hdmi/hdmi/serializer/gwSer1</td>
</tr>
<tr>
<td>40.727</td>
<td>-0.153</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT68[A]</td>
<td>u_hdmi/hdmi/serializer/gwSer1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.291</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>40.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.908, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.382, 86.632%; tC2Q: 0.368, 13.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.915, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.548</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.548</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C14[2][A]</td>
<td style=" font-weight:bold;">nes/multi_mapper/map69/chr_bank[0]_ER_init_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.702</td>
<td>0.404</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C14[2][A]</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s1/CLK</td>
</tr>
<tr>
<td>1.737</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s1</td>
</tr>
<tr>
<td>1.548</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C14[2][A]</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.702</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.404, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.543</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>spin_state_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>spin_state_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C41[0][A]</td>
<td style=" font-weight:bold;">spin_state_s2/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.697</td>
<td>0.399</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C41[0][A]</td>
<td>spin_state_s2/CLK</td>
</tr>
<tr>
<td>1.732</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spin_state_s2</td>
</tr>
<tr>
<td>1.543</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C41[0][A]</td>
<td>spin_state_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.697</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.399, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.541</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.541</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23[1][A]</td>
<td style=" font-weight:bold;">nes/multi_mapper/map69/chr_bank[0]_ER_init_s/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.694</td>
<td>0.397</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C23[1][A]</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s/CLK</td>
</tr>
<tr>
<td>1.729</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s</td>
</tr>
<tr>
<td>1.541</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C23[1][A]</td>
<td>nes/multi_mapper/map69/chr_bank[0]_ER_init_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.694</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.397, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.522</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>memory/u_sdram/cycle_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>memory/u_sdram/cycle_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C35[2][A]</td>
<td style=" font-weight:bold;">memory/u_sdram/cycle_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.675</td>
<td>0.377</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C35[2][A]</td>
<td>memory/u_sdram/cycle_0_s0/CLK</td>
</tr>
<tr>
<td>1.710</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>memory/u_sdram/cycle_0_s0</td>
</tr>
<tr>
<td>1.522</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C35[2][A]</td>
<td>memory/u_sdram/cycle_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.675</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.377, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.521</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.521</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s25</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s25</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C74[1][B]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s25/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.675</td>
<td>0.377</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C74[1][B]</td>
<td>sd_loader/menu_color_4_s25/CLK</td>
</tr>
<tr>
<td>1.710</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s25</td>
</tr>
<tr>
<td>1.521</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C74[1][B]</td>
<td>sd_loader/menu_color_4_s25</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.675</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.377, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.519</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.519</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/active_2_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/active_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C78[0][A]</td>
<td style=" font-weight:bold;">sd_loader/active_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.673</td>
<td>0.375</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C78[0][A]</td>
<td>sd_loader/active_2_s1/CLK</td>
</tr>
<tr>
<td>1.708</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/active_2_s1</td>
</tr>
<tr>
<td>1.519</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C78[0][A]</td>
<td>sd_loader/active_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.673</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.375, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.519</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.519</td>
</tr>
<tr>
<td class="label">From</td>
<td>state_1_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>state_1_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C42[0][B]</td>
<td style=" font-weight:bold;">state_1_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.673</td>
<td>0.375</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C42[0][B]</td>
<td>state_1_0_s0/CLK</td>
</tr>
<tr>
<td>1.708</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>state_1_0_s0</td>
</tr>
<tr>
<td>1.519</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C42[0][B]</td>
<td>state_1_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.673</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.375, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.519</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.519</td>
</tr>
<tr>
<td class="label">From</td>
<td>state_0_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>state_0_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C42[0][A]</td>
<td style=" font-weight:bold;">state_0_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.673</td>
<td>0.375</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C42[0][A]</td>
<td>state_0_0_s0/CLK</td>
</tr>
<tr>
<td>1.708</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>state_0_0_s0</td>
</tr>
<tr>
<td>1.519</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C42[0][A]</td>
<td>state_0_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.673</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.375, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.518</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.518</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s8</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s8</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C74[2][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s8/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.672</td>
<td>0.374</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C74[2][A]</td>
<td>sd_loader/menu_color_4_s8/CLK</td>
</tr>
<tr>
<td>1.707</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s8</td>
</tr>
<tr>
<td>1.518</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C74[2][A]</td>
<td>sd_loader/menu_color_4_s8</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.672</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.374, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.517</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.517</td>
</tr>
<tr>
<td class="label">From</td>
<td>memory/u_sdram/cycle_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>memory/u_sdram/cycle_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C36[0][A]</td>
<td style=" font-weight:bold;">memory/u_sdram/cycle_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.670</td>
<td>0.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C36[0][A]</td>
<td>memory/u_sdram/cycle_3_s0/CLK</td>
</tr>
<tr>
<td>1.705</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>memory/u_sdram/cycle_3_s0</td>
</tr>
<tr>
<td>1.517</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C36[0][A]</td>
<td>memory/u_sdram/cycle_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.670</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.373, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.517</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.517</td>
</tr>
<tr>
<td class="label">From</td>
<td>memory/u_sdram/cycle_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>memory/u_sdram/cycle_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C36[1][A]</td>
<td style=" font-weight:bold;">memory/u_sdram/cycle_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.670</td>
<td>0.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C36[1][A]</td>
<td>memory/u_sdram/cycle_1_s0/CLK</td>
</tr>
<tr>
<td>1.705</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>memory/u_sdram/cycle_1_s0</td>
</tr>
<tr>
<td>1.517</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C36[1][A]</td>
<td>memory/u_sdram/cycle_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.670</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.373, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.517</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.517</td>
</tr>
<tr>
<td class="label">From</td>
<td>memory/u_sdram/cycle_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>memory/u_sdram/cycle_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C36[0][B]</td>
<td style=" font-weight:bold;">memory/u_sdram/cycle_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.670</td>
<td>0.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C36[0][B]</td>
<td>memory/u_sdram/cycle_2_s0/CLK</td>
</tr>
<tr>
<td>1.705</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>memory/u_sdram/cycle_2_s0</td>
</tr>
<tr>
<td>1.517</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C36[0][B]</td>
<td>memory/u_sdram/cycle_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.670</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.373, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.514</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.514</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s39</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s39</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C73[2][B]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s39/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.668</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C73[2][B]</td>
<td>sd_loader/menu_color_4_s39/CLK</td>
</tr>
<tr>
<td>1.703</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s39</td>
</tr>
<tr>
<td>1.514</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C73[2][B]</td>
<td>sd_loader/menu_color_4_s39</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.668</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.370, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.514</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.514</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s27</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s27</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C75[2][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s27/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.668</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C75[2][A]</td>
<td>sd_loader/menu_color_4_s27/CLK</td>
</tr>
<tr>
<td>1.703</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s27</td>
</tr>
<tr>
<td>1.514</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C75[2][A]</td>
<td>sd_loader/menu_color_4_s27</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.668</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.370, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.514</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.514</td>
</tr>
<tr>
<td class="label">From</td>
<td>print_buffer_906_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>print_buffer_906_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C41[1][A]</td>
<td style=" font-weight:bold;">print_buffer_906_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.668</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C41[1][A]</td>
<td>print_buffer_906_s1/CLK</td>
</tr>
<tr>
<td>1.703</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>print_buffer_906_s1</td>
</tr>
<tr>
<td>1.514</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C41[1][A]</td>
<td>print_buffer_906_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.668</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.370, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.514</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.514</td>
</tr>
<tr>
<td class="label">From</td>
<td>print_buffer_866_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>print_buffer_866_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C41[1][B]</td>
<td style=" font-weight:bold;">print_buffer_866_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.668</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C41[1][B]</td>
<td>print_buffer_866_s1/CLK</td>
</tr>
<tr>
<td>1.703</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>print_buffer_866_s1</td>
</tr>
<tr>
<td>1.514</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C41[1][B]</td>
<td>print_buffer_866_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.668</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.370, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.514</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.514</td>
</tr>
<tr>
<td class="label">From</td>
<td>memory/u_sdram/rst_done_p1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>memory/u_sdram/rst_done_p1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C34[1][A]</td>
<td style=" font-weight:bold;">memory/u_sdram/rst_done_p1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.668</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C34[1][A]</td>
<td>memory/u_sdram/rst_done_p1_s0/CLK</td>
</tr>
<tr>
<td>1.703</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>memory/u_sdram/rst_done_p1_s0</td>
</tr>
<tr>
<td>1.514</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C34[1][A]</td>
<td>memory/u_sdram/rst_done_p1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.668</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.370, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.513</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s14</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s14</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[0][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s14/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.667</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[0][A]</td>
<td>sd_loader/menu_color_4_s14/CLK</td>
</tr>
<tr>
<td>1.702</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s14</td>
</tr>
<tr>
<td>1.513</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C75[0][A]</td>
<td>sd_loader/menu_color_4_s14</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.667</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.369, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.513</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s10</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[0][B]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s10/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.667</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[0][B]</td>
<td>sd_loader/menu_color_4_s10/CLK</td>
</tr>
<tr>
<td>1.702</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s10</td>
</tr>
<tr>
<td>1.513</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C75[0][B]</td>
<td>sd_loader/menu_color_4_s10</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.667</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.369, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.513</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s6</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s6</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C73[3][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s6/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.667</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C73[3][A]</td>
<td>sd_loader/menu_color_4_s6/CLK</td>
</tr>
<tr>
<td>1.702</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s6</td>
</tr>
<tr>
<td>1.513</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C73[3][A]</td>
<td>sd_loader/menu_color_4_s6</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.667</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.369, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.513</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[1][B]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s4/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.667</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[1][B]</td>
<td>sd_loader/menu_color_4_s4/CLK</td>
</tr>
<tr>
<td>1.702</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s4</td>
</tr>
<tr>
<td>1.513</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C75[1][B]</td>
<td>sd_loader/menu_color_4_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.667</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.369, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.513</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[1][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s2/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.667</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C75[1][A]</td>
<td>sd_loader/menu_color_4_s2/CLK</td>
</tr>
<tr>
<td>1.702</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s2</td>
</tr>
<tr>
<td>1.513</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C75[1][A]</td>
<td>sd_loader/menu_color_4_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.667</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.369, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.513</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_demux/state_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_demux/state_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C31[0][A]</td>
<td style=" font-weight:bold;">uart_demux/state_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.667</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C31[0][A]</td>
<td>uart_demux/state_0_s1/CLK</td>
</tr>
<tr>
<td>1.702</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>uart_demux/state_0_s1</td>
</tr>
<tr>
<td>1.513</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C31[0][A]</td>
<td>uart_demux/state_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.667</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.369, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.509</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.509</td>
</tr>
<tr>
<td class="label">From</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[3][A]</td>
<td style=" font-weight:bold;">nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.663</td>
<td>0.365</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[3][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s/CLK</td>
</tr>
<tr>
<td>1.698</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s</td>
</tr>
<tr>
<td>1.509</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C17[3][A]</td>
<td>nes/ppu/sprite_ram/oam_8708_DIAREG_G_5_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.663</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.365, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.508</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.508</td>
</tr>
<tr>
<td class="label">From</td>
<td>sd_loader/menu_color_4_s38</td>
</tr>
<tr>
<td class="label">To</td>
<td>sd_loader/menu_color_4_s38</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk_sdram:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk_sdram</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>5561</td>
<td>-</td>
<td>GND_cZ/G</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C73[0][A]</td>
<td style=" font-weight:bold;">sd_loader/menu_color_4_s38/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>pll_clk/PLLA_inst/CLKOUT3.default_gen_clk</td>
</tr>
<tr>
<td>1.298</td>
<td>1.298</td>
<td>tCL</td>
<td>RR</td>
<td>3685</td>
<td>PLL_L[1]</td>
<td>pll_clk/PLLA_inst/CLKOUT3</td>
</tr>
<tr>
<td>1.662</td>
<td>0.364</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C73[0][A]</td>
<td>sd_loader/menu_color_4_s38/CLK</td>
</tr>
<tr>
<td>1.697</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>sd_loader/menu_color_4_s38</td>
</tr>
<tr>
<td>1.508</td>
<td>-0.189</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R32C73[0][A]</td>
<td>sd_loader/menu_color_4_s38</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.662</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.364, 100.000%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.302</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.552</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller/W_rxd_mask_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>8.410</td>
<td>3.410</td>
<td>tNET</td>
<td>FF</td>
<td>controller/W_rxd_mask_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller/W_scan_seq_pls</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q</td>
</tr>
<tr>
<td>11.962</td>
<td>1.963</td>
<td>tNET</td>
<td>RR</td>
<td>controller/W_rxd_mask_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.794</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.044</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller2/rxd/O_RXD_DAT_2_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>2.196</td>
<td>2.196</td>
<td>tNET</td>
<td>RR</td>
<td>controller2/rxd/O_RXD_DAT_2_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>6.239</td>
<td>1.239</td>
<td>tNET</td>
<td>FF</td>
<td>controller2/rxd/O_RXD_DAT_2_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.796</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.046</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller2/O_RXD_1_7_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>2.203</td>
<td>2.203</td>
<td>tNET</td>
<td>RR</td>
<td>controller2/O_RXD_1_7_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>6.249</td>
<td>1.249</td>
<td>tNET</td>
<td>FF</td>
<td>controller2/O_RXD_1_7_s1/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.796</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.046</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller2/O_RXD_1_6_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>2.203</td>
<td>2.203</td>
<td>tNET</td>
<td>RR</td>
<td>controller2/O_RXD_1_6_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>6.249</td>
<td>1.249</td>
<td>tNET</td>
<td>FF</td>
<td>controller2/O_RXD_1_6_s1/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.796</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.046</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller2/O_RXD_2_6_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>2.203</td>
<td>2.203</td>
<td>tNET</td>
<td>RR</td>
<td>controller2/O_RXD_2_6_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>6.249</td>
<td>1.249</td>
<td>tNET</td>
<td>FF</td>
<td>controller2/O_RXD_2_6_s1/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.796</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.046</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller2/O_RXD_2_5_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>2.203</td>
<td>2.203</td>
<td>tNET</td>
<td>RR</td>
<td>controller2/O_RXD_2_5_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>6.249</td>
<td>1.249</td>
<td>tNET</td>
<td>FF</td>
<td>controller2/O_RXD_2_5_s1/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.796</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.046</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller2/rxd/O_RXD_DAT_7_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>2.181</td>
<td>2.181</td>
<td>tNET</td>
<td>RR</td>
<td>controller2/rxd/O_RXD_DAT_7_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>6.227</td>
<td>1.228</td>
<td>tNET</td>
<td>FF</td>
<td>controller2/rxd/O_RXD_DAT_7_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.796</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.046</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller2/rxd/O_RXD_DAT_6_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>2.181</td>
<td>2.181</td>
<td>tNET</td>
<td>RR</td>
<td>controller2/rxd/O_RXD_DAT_6_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>6.227</td>
<td>1.228</td>
<td>tNET</td>
<td>FF</td>
<td>controller2/rxd/O_RXD_DAT_6_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.796</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.046</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller2/rxd/O_RXD_DAT_3_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>2.181</td>
<td>2.181</td>
<td>tNET</td>
<td>RR</td>
<td>controller2/rxd/O_RXD_DAT_3_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>6.227</td>
<td>1.228</td>
<td>tNET</td>
<td>FF</td>
<td>controller2/rxd/O_RXD_DAT_3_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.798</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.048</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>controller2/rxd/O_RXD_DAT_5_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>2.171</td>
<td>2.171</td>
<td>tNET</td>
<td>RR</td>
<td>controller2/rxd/O_RXD_DAT_5_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>controller2/n50_15</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>controller2/n50_s1/F</td>
</tr>
<tr>
<td>6.219</td>
<td>1.219</td>
<td>tNET</td>
<td>FF</td>
<td>controller2/rxd/O_RXD_DAT_5_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>5561</td>
<td>GND</td>
<td>-1.856</td>
<td>0.876</td>
</tr>
<tr>
<td>3685</td>
<td>clk</td>
<td>-4.081</td>
<td>0.929</td>
</tr>
<tr>
<td>1221</td>
<td>n17855_5</td>
<td>28.897</td>
<td>7.491</td>
</tr>
<tr>
<td>933</td>
<td>loader_done</td>
<td>25.935</td>
<td>4.857</td>
</tr>
<tr>
<td>824</td>
<td>VCC</td>
<td>-1.370</td>
<td>0.938</td>
</tr>
<tr>
<td>728</td>
<td>clk_p</td>
<td>9.028</td>
<td>1.051</td>
</tr>
<tr>
<td>392</td>
<td>clk_usb</td>
<td>-5.066</td>
<td>0.913</td>
</tr>
<tr>
<td>370</td>
<td>sys_resetn</td>
<td>-4.081</td>
<td>2.906</td>
</tr>
<tr>
<td>286</td>
<td>n28161_4</td>
<td>28.024</td>
<td>4.169</td>
</tr>
<tr>
<td>265</td>
<td>sample_buffer_current_6</td>
<td>34.259</td>
<td>2.807</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R15C68</td>
<td>61.11%</td>
</tr>
<tr>
<td>R27C67</td>
<td>61.11%</td>
</tr>
<tr>
<td>R27C69</td>
<td>61.11%</td>
</tr>
<tr>
<td>R29C30</td>
<td>61.11%</td>
</tr>
<tr>
<td>R29C31</td>
<td>61.11%</td>
</tr>
<tr>
<td>R29C76</td>
<td>61.11%</td>
</tr>
<tr>
<td>R29C69</td>
<td>59.72%</td>
</tr>
<tr>
<td>R28C68</td>
<td>59.72%</td>
</tr>
<tr>
<td>R34C78</td>
<td>58.33%</td>
</tr>
<tr>
<td>R30C70</td>
<td>58.33%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name sys_clk -period 20 -waveform {0 10} [all_inputs]</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name clk_sdram -period 40 -waveform {0 20} [all_outputs]</td>
</tr>
</table>
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